The present invention relates generally to a semiconductor memory such as a DRAM etc. and, more particularly, to a semiconductor memory including redundancy memory cells with which defective cells in the body memory can be replaced.
The semiconductor memory is unusable as a product if all the memory cells do not normally function. Providing that the semiconductor memory having the regular memory cells which are all normal is treated as a good-quality memory, however, the yield might decrease. The semiconductor memory is therefore provided beforehand with redundancy memory cells as preparatory memory cells in addition to the regular memory cells, and, if there occurs a regular memory cell which does not normally function, the redundancy memory cell is utilized by the defective memory cell being electrically replaced with this redundancy memory cell.
The defective memory cell contained in the regular memory cells is detected in a wafer test at a stage before a wafer is sliced into chips (dies) of the individual semiconductor memories. The wafer test for the semiconductor memory is classified into two stages, i.e., a primary inspection (a pre-wafer test) for examining whether or not the regular memory cells normally function and judging, if there is a defective cell, whether or not this defective cell can be replaced with the redundancy memory cell, and a secondary inspection (a final wafer test) for examining after a necessary replacing process (a defect repairing process) whether or not the memory cell normally functions in an as-replaced state.
As a result of the primary inspection, the tested semiconductor memories are classified into three groups such as a group (1) in which all the regular memory cells exhibit a normal good quality, a group (2) in which some of the regular memory cells are defective, and the chip is still repairable by replacing the defective cells with the redundancy cells, and a group (3) containing unrepairable defects such that the defective cells among the regular memory cells are numerous enough not to be replaceable with the redundancy memory cells.
The primary and secondary inspections each include a plurality of item tests. The memory classified into the defective memory group (3) is disposed of after being sliced into the chips, and therefore an implementation of the secondary inspection for the memory of this group (3) leads to a futile expansion of the testing time. Such being the case, the semiconductor memory provided with a defect identification fuse within a circuit is disclosed in, e.g., Japanese Patent Application Laid-Open Publication Nos.5-47862 and 7-30068.
If the defect identification fuse disclosed in those Publications is used, in the memory classified into the defect memory group (3) as a result of the primary inspection, the identification fuse is cut off, and state of the identification fuse is detected at first in the secondary inspection, whereby the test for the memory with the identification fuse cut off is discontinued upon cutting off this fuse, and the test can be shifted to a next memory. Note that in the embodiment disclosed in Japanese Patent Application Laid-Open Publication No.5-47862, the identification fuse is provided between a GND terminal and dummy terminal. Japanese Patent Application Laid-Open Publication No.7-30068 does not disclose which position the identification fuse is disposed within the semiconductor memory.
A first problem inherent in the prior art described above is that there is no disclosure about a relationship between a position of the fuse for designating the replacement of the defective regular memory cell with the redundancy memory cell and a position of the identification fuse. Each fuse is cut off according to the necessity by a laser by use of a repair device when in the replacing process, however, precise positioning per chip is indispensable for cutting off the fuse provided in a more minute region than and within the hyperfine chip. Accordingly, if the positional relationship between the fuse for designating the replacement and the identification fuse is not specified as in the devices disclosed in the above Publications, there must be a necessity for positioning for cutting off each of the designation fuse and the identification fuse, and the yield in the replacement process therefore declines.
A second problem inherent in the prior art is that it is possible to only distinguish between the good-quality chip and the defective chip in terms of a state of the identification fuse, but it is impossible to distinguish what kind of error occurs with respect to the chip judged to be defective. Information on such a defective chip is recorded in a test record (LOG) and fed back to the manufacturing process in order to enhance the yield, and then a measure is to be taken. The LOG is, however, managed with only a serial number of the wafer, and hence it might become unobvious in some cases to grasp what kind of defect appears in the chip, and which position the chip concerned is disposed within the wafer. In such a case, no measure can be taken.
A third problem inherent in the prior art is that the fuse dedicated to the identification is provided separately from the address designation fuse, and therefore the number of fuses is larger than in the device having no identification fuse.
To obviate the above-described first problem inherent in the prior art, a first object of the invention in the present application is to provide a semiconductor memory in which a repair device can be easily positioned with respect to a redundancy fuse for a designation of replacement and a defect identification fuse when in a replacing process.
To obviate the above-described second problem inherent in the prior art, a second object of the invention in the present application is to provide a semiconductor memory capable of not only distinguishing between a good-quality chip and a defective chip but also judging what kind of error occurs in the case of the defective chip.
To obviate the above-described third problem inherent in the prior art, a third object of the invention is to provide a semiconductor memory capable of distinguishing between the good-quality chip and the defective chip in a secondary inspection without providing a fuse dedicated to an identification.